1. Field of Invention
This invention pertains generally to semiconductor memory devices and, more particularly, to a NAND flash memory and process of fabricating the same.
2. Related Art
Nonvolatile memory is currently available in several forms, including electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and flash EEPROM. Flash memory has been widely used for high volume data storage in devices such as memory cards, personal digital assistants (PDA's), cellular phones, and MP3 players. Such applications require high density memory, with smaller cell size and reduced cost of manufacture.
The traditional NOR-type stack-gate flash memory cell usually has a bit line contact, a source region, a floating gate, and a control gate, with the control gate being positioned directly above the floating gate. Its relatively large cell size prevents it from being used in very high density data storage applications.
Cell size is smaller in a NAND flash memory array having a series of stack-gate flash memory cells connected in series between a bit-line and a source line, with only one bit-line contact, as illustrated in FIG. 1 and described in greater detail in U.S. Pat. Nos. 4,959,812 and 5,050,125. In this array, a plurality of stack-gate memory cells 21 are connected in series between a bit line diffusion 22 and a source diffusion 23. The cells are formed in a P-well 24 in a substrate 26 of either N- or P-type silicon. Each of the cells has a floating gate 27 fabricated of a conductive material such as polysilicon and a control gate 28 fabricated of a conductive material such as polysilicon or polycide. The control gate is above and in vertical alignment with the floating gate.
Two select gates 29, 30 are included in the array, one near the bit line diffusion 22 and one near source diffusion 23. The bit line 31 for each row is connected to the bit line diffusion by a bit line contact 32 contact. Diffusions 33 are formed in the substrate between the stacked gates and between the stacked gates and the select gates to serve as source and drain regions for the transistors in the memory cells. The bit line diffusions, source diffusion, and diffusions 33 are doped with N-type dopants.
To erase the memory cell, a positive voltage of about 20 volts is applied between the P-well and the control gates, which causes the electrons to tunnel from the floating gates to the channel regions beneath them. The floating gates thus become positively charged, and the threshold voltage of the stack-gate cells becomes negative.
To program the memory cells, the control gates are biased to a level of about 20 volts positive relative to the P-well. As electrons tunnel from the channel region to the floating gates, the floating gates are negatively charged, and the threshold voltage of the stack-gate cells becomes positive. By changing the threshold voltage of a stack-gate cell, the channel beneath it can be in either a non-conduction state (logical) or a conduction state (logical when a zero voltage is applied to the control gate during a read operation.
However, as the fabrication process advances to very smaller geometry, e.g., tens of nanometer, it is difficult to form a high-voltage coupling ratio which is sufficient for program and erase operations while maintaining a small cell size.